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ads8320-ht www.ti.com sbas521b ? december 2010 ? revised september 2012 16-bit, high-speed, 2.7-v to 5-v, micropower sampling analog-to-digital converter check for samples: ads8320-ht 1 features supports extreme temperature applications 2 ? 100-khz sampling rate ? controlled baseline ? micropower: ? one assembly/test site ? 3.8 mw at 100 khz and 2.7 v ? one fabrication site ? 0.3 mw at 10 khz and 2.7 v ? available in extreme ( ? 55 c/210 c) ? power down: 6 a max temperature range (1) ? 8-pin ceramic package ? extended product life cycle ? pin compatible to ads7816 and ads7822 ? extended product-change notification ? serial ( spi ? /ssi) interface ? product traceability applications ? texas instruments' high temperature products utilize highly optimized silicon (die) solutions ? down-hole drilling with design and process enhancements to ? high temperature environments maximize performance over extended ? vibration/modal analysis temperatures. ? multi-channel data acquisition ? acoustics/dynamic strain gauges ? pressure sensors (1) custom temperature ranges available description the ads8320 is a 16-bit, sampling analog-to-digital (a/d) converter with ensured specifications over a 2.7-v to 5.25-v supply range. it requires very little power even when operating at the full 100-khz data rate. at lower data rates, the high speed of the device enables it to spend most of its time in the power-down mode ? the average power dissipation is less than 100 mw at 10-khz data rate. the ads8320 also features operation from 2 v to 5.25 v, a synchronous serial (spi/ssi compatible) interface, and a differential input. the reference voltage can be set to any level within the range of 500 mv to v cc . ultra-low power and small size make the ads8320 ideal for portable and battery-operated systems. it is also a perfect fit for remote data acquisition modules, simultaneous multi-channel systems, and isolated data acquisition. the ads8320 is available in 8-pin ceramic surface-mount packages, specified for the ? 55 c to 210 c temperature range. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 spi is a trademark of motorola, inc.. production data information is current as of publication date. copyright ? 2010 ? 2012, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. sar control d out comparator s/h amp cs/shdn dclock +in v ref Cin cdac serial interface
ads8320-ht sbas521b ? december 2010 ? revised september 2012 www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ordering information (1) orderable part t a package top-side marking package qty | carrier number hkj ads8320shkj ads8320shkj 1 | tube hkq ADS8320SHKQ ADS8320SHKQ 1 | tube ? 55 c to 210 c ads8320skgd1 na 240 | tray kgd ads8320skgd2 na 10 | tray (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti web site at www.ti.com . bare die information backside bond pad die thickness backside finish potential metallization composition 15 mils silicon backgrind gnd al-si-cu 2 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: ads8320-ht a b c d origin
ads8320-ht www.ti.com sbas521b ? december 2010 ? revised september 2012 table 1. bond pad coordinates in microns - rev a discription pad number a b c d vref 1 157.3 1437.4 259.5 1669.6 +in 2 157.3 1149.4 256.6 1248.7 -in 3 157.3 432.3 256.6 531.6 gnd 4 171.2 137.4 270.4 366.6 cs/shdn 5 1183.1 141.3 1282.4 240.6 dout 6 1183.1 448.6 1282.4 547.8 dclock 7 1183.1 1011.1 1282.4 1110.4 +vcc 8 1183.1 1462.8 1282.4 1692 copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 3 product folder links: ads8320-ht vref +in -in gnd csn/shdn dout dclock +vcc
ads8320-ht sbas521b ? december 2010 ? revised september 2012 www.ti.com absolute maximum ratings over operating free-air temperature range (unless otherwise noted). (1) unit v cc 6 v analog input voltage -0.3 to 6 v case temperature 100 c junction temperature ? 55 to 210 c storage temperature ? 55 to 210 c external referance voltage 5.5 v input current to any pin except supply 10 ma (1) stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. thermal characteristics for hkj or hkq package over operating free-air temperature range (unless otherwise noted) parameter min typ max unit to ceramic side of case 5.7 jc junction-to-case thermal resistance c/w to top of case lid (metal side of case) 13.7 electrical characteristics v cc = 2.7 v , v ref = 2.5 v, -in = gnd, f sample = 100 khz and f clk = 24 x f sample , unless otherwise noted. conditions t a = -55 c to 125 c t a = 210 c (1) unit parameter min typ max min typ max resolution 16 16 bits analog input full-zcale input span +in ? ( ? in) 0 vref 0 vref v +in ? 0.1 vcc + 0.1 ? 0.1 vcc + 0.1 absolute input range v ? in ? 0.1 0.5 ? 0.1 0.5 capacitance 45 45 pf leakage current 1 1 na system performance no missing codes 14 14 bits integral linearity error 0.008 0.032 0.018 0.034 % of fsr offset error v in = 3 v 0.6 3.8 0.5 3.8 mv offset temperature drift v in = 3 v 3 4 v/ c gain error v in = 3 v 0.05 0.05 % of fsr gain temperature drift v in = 3 v 0.3 0.3 ppm/ c noise 20 21 vrms power-supply rejection ratio 2.7 v < v cc < 3.3 v 3 5 lsb (2) (1) minimum and maximum parameters are characterized for operation at t a = 210 c, but may not be production tested at that temperature. production test limits with statistical guardbands are used to ensure high temperature performance. (2) lsb means least significant bit. with v ref = 2.5 v, one lsb is 0.038 v. 4 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: ads8320-ht
ads8320-ht www.ti.com sbas521b ? december 2010 ? revised september 2012 electrical characteristics (continued) v cc = 2.7 v , v ref = 2.5 v, -in = gnd, f sample = 100 khz and f clk = 24 x f sample , unless otherwise noted. conditions t a = -55 c to 125 c t a = 210 c (1) unit parameter min typ max min typ max sampling dynamics conversion time 16 16 clk cycles acquisition time 4.5 4.5 clk cycles throughput rate 100 100 khz clock frequency range 0.02 2.4 0.02 2.4 mhz dynamic characteristics total harmonic distortion v in = 2.7 x vp-p at 1 khz -86 -82 db sinad v in = 2.7 x vp-p at 1 khz 84 79 db spurious-free dynamic range v in = 2.7 x vp-p at 1 khz 86 82 db snr 88 83 db reference input voltage range 0.5 v cc 0.5 v cc v cs = gnd, f sample = 0 hz 5 5 resistance g cs = v cc 5 5 20 50 25 55 current drain a cs = v cc 0.1 7 0.9 12 digital input/output logic family cmos cmos v ih i ih = 5 a 2 v cc + 0.3 2 v cc + 0.3 v v il i il = 5 a -0.3 0.8 -0.3 0.8 v logic levels v oh i oh = ? 250 a 2.1 2.1 v v ol i ol = 250 a 0.4 0.4 v data format straight binary power supply requirements v cc specified performance 2.7 3.3 2.7 3.3 v 2 5.25 2 5.25 v cc range (3) v see (4) 2 2.7 2 2.7 850 1300 650 1300 quiescent current a f sample = 10 khz (5) (6) 100 100 power dissipation 2.3 3.8 1.75 3.8 mw power-down cs = v cc 0.3 4 6 a temperature range specified performance -55 125 -55 210 c (3) see the typical performance curves for more information. (4) the maximum clock rate of the ads8320 is less than 2.4 mhz in this power supply range. (5) f clk = 2.4 mhz, cs = v cc for 216 clock cycles out of every 240. (6) see the power dissipation section for more information regarding lower sample rates. copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 5 product folder links: ads8320-ht
ads8320-ht sbas521b ? december 2010 ? revised september 2012 www.ti.com electrical characteristics v cc = 5 v , v ref = 5 v, -in = gnd, f sample = 100 khz and f clk = 24 x f sample , unless otherwise noted. conditions t a = -55 c to 125 c t a = 210 c (1) unit parameter min typ max min typ max resolution 16 16 bits analog input full-zcale input span +in ? ( ? in) 0 vref 0 vref v +in ? 0.1 vcc + 0.1 ? 0.1 vcc + 0.1 absolute input range v ? in ? 0.1 0.5 ? 0.1 0.5 capacitance 45 45 pf leakage current 1 1 na system performance no missing codes 14 14 bits integral linearity error 0.008 0.032 0.018 0.034 % of fsr offset error 0.6 3.8 0.5 3.8 mv offset temperature drift 3 4 v/ c gain error 0.05 0.05 % of fsr gain temperature drift 0.3 0.3 ppm/ c noise 20 21 vrms power-supply rejection ratio 4.7 v < v cc < 5.25 v 3 35 lsb (2) sampling dynamics conversion time 16 16 clk cycles acquisition time 4.5 4.5 clk cycles throughput rate 100 100 khz clock frequency range 0.02 2.4 0.02 2.4 mhz dynamic characteristics total harmonic distortion v in = 5 x vp-p at 10 khz -84 -83 db sinad v in = 5 x vp-p at 10 khz 82 81 db spurious-free dynamic range v in = 5 x vp-p at 10 khz 84 83 db snr 90 88 db reference input voltage range 0.5 v cc 0.5 v cc v cs = gnd, f sample = 0 hz 5 5 resistance g cs = v cc 5 5 40 80 50 80 current drain f sample = 10 khz 0.8 0.8 a cs = v cc 0.1 5 2 5 digital input/output logic family cmos cmos v ih i ih = 5 a 3 v cc + 0.3 3 v cc + 0.3 v v il i il = 5 a -0.3 0.8 -0.3 0.8 v logic levels v oh i oh = ? 250 a 4 4 v v ol i ol = 250 a 0.4 0.4 v data format straight binary (1) minimum and maximum parameters are characterized for operation at t a = 210 c, but may not be production tested at that temperature. production test limits with statistical guardbands are used to ensure high temperature performance. (2) lsb means least significant bit. with v ref = 5 v, one lsb is 0.076 v. 6 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: ads8320-ht
ads8320-ht www.ti.com sbas521b ? december 2010 ? revised september 2012 electrical characteristics (continued) v cc = 5 v , v ref = 5 v, -in = gnd, f sample = 100 khz and f clk = 24 x f sample , unless otherwise noted. conditions t a = -55 c to 125 c t a = 210 c (1) unit parameter min typ max min typ max power supply requirements v cc specified performance 4.75 5.25 4.75 5.25 v v cc range (3) 2 5.25 2 5.25 v 1150 1700 850 1700 quiescent current a f sample = 10 khz (4) (5) 200 200 power dissipation 5.5 8.5 4.5 8.5 mw power-down cs = v cc 0.3 3 5 a temperature range specified performance -55 125 -55 210 c (3) see the typical performance curves for more information. (4) f clk = 2.4 mhz, cs = v cc for 216 clock cycles out of every 240. (5) see the power dissipation section for more information regarding lower sample rates. pin configuration pin assignments pin # name description 1 v ref reference input 2 +in noninverting input 3 -in inverting input. connect to ground or to remote ground sense point. 4 gnd ground 5 cs/shdn chip select when low, shutdown mode when high. the serial output data word is comprised of 16 bits of data. in operation the data is valid on the falling edge of dclock. the 6 d out second clock pulse after the falling edge of cs enables the serial output. after one null bit the data is valid for the next 16 edges. 7 dclock data clock synchronizes the serial data transfer and determines conversion speed. 8 +v cc power supply copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 7 product folder links: ads8320-ht hkq package (top view) 8 5 4 1 hkq as formed or hkj mounted dead bug v ref +in -in gnd +v cc dclock d out cs/shdn 12 3 4 87 6 5 +v cc dclockd out cs/shdn v ref +in Cin gnd ads8320 hkj package (top view)
ads8320-ht sbas521b ? december 2010 ? revised september 2012 www.ti.com xxx typical characteristics at t a = 25 c, v cc = 5 v, v ref = 5 v, f sample = 100 khz, and f clk = 24 x f sample , unless otherwise specified. integral linearity error differential linearity error vs vs code (25 c) code (25 c) figure 1. figure 2. supply current power-down supply current vs vs temperature temperature figure 3. figure 4. 8 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: ads8320-ht 0 200 400 600 800 1000 1200 1400 ?55 0 55 110 165 220 temperature (c) supply current (a) 5v 2.7v ?1000 0 1000 2000 3000 4000 5000 6000 ?55 0 55 110 165 220 temperature (c) supply current (na) 5v 2 01.0 0.0 C1.0 C2.0 C3.0 C4.0 C5.0 C6.0 integral linearity error (lsb) 0000 h 8000 h c000 h 4000 h ffff h hex code 3.02.0 1.0 0.0 C1.0 C2.0 C3.0 differential linearity error (lsb) 0000 h 8000 h c000 h 4000 h ffff h hex code
ads8320-ht www.ti.com sbas521b ? december 2010 ? revised september 2012 typical characteristics (continued) at t a = 25 c, v cc = 5 v, v ref = 5 v, f sample = 100 khz, and f clk = 24 x f sample , unless otherwise specified. quiescent current maximum sample rate vs vs v cc v cc figure 5. figure 6. change in offset change in offset vs vs reference voltage temperature figure 7. figure 8. change in gain change in gain vs vs reference voltage temperature figure 9. figure 10. copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 9 product folder links: ads8320-ht ?55 0 55 110 165 220 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 temperature (c) delta from 25c (lsb) 2.7v 5v 54 3 2 1 0 C1 C2 change in gain (lsb) 1 2 3 4 5 reference voltage (v) v cc = 5v ?55 0 55 110 165 220 ?6 ?5 ?4 ?3 ?2 ?1 0 1 temperature (c) delta from 25c (lsb) 2.7v 5v 65 4 3 2 1 0 C1 C2 C3 change in offset (lsb) 1 2 3 4 5 reference voltage (v) v cc = 5v 1200 1000 800 600 400 200 quiescent current (a) 1 2 3 4 5 v cc (v) 1000 100 10 1 sample rate (khz) 1 2 3 4 5 v cc (v)
ads8320-ht sbas521b ? december 2010 ? revised september 2012 www.ti.com typical characteristics (continued) at t a = 25 c, v cc = 5 v, v ref = 5 v, f sample = 100 khz, and f clk = 24 x f sample , unless otherwise specified. peak-to-peak noise frequency spectrum vs (8192 point fft, f in = 10.120 khz, ? 0.3 db) reference voltage figure 11. figure 12. spurious-free dynamic range and signal-to- noise ratio total harmonic distortion vs vs frequency frequency figure 13. figure 14. 10 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: ads8320-ht 100 90 80 70 60 50 40 30 20 10 0 spurious-free dynamic range and signal-to-noise ratio (db) 50 frequency (khz) signal-to-noise ratio spurious-free dynamic range 1 10 100 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 total harmonic distortion (db) frequency (khz) 1 10 100 0 C20 C40 C60 C80 C100 C120 C140 amplitude (db) frequency (khz) 0 10 20 30 40 50 10 98 7 6 5 4 3 2 1 0 peak-to-peak noise (lsb) reference voltage (v) v cc = 5v 0.1 1 10
ads8320-ht www.ti.com sbas521b ? december 2010 ? revised september 2012 typical characteristics (continued) at t a = 25 c, v cc = 5 v, v ref = 5 v, f sample = 100 khz, and f clk = 24 x f sample , unless otherwise specified. signal-to-(noise + distortion) signal-to-(noise + distortion) vs vs frequency input level figure 15. figure 16. reference current reference current vs vs sample rate temperature figure 17. figure 18. copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 11 product folder links: ads8320-ht 70 60 50 40 30 20 10 0 reference current (a) sample rate (khz) 5v 2.7v 0 20 40 60 80 100 100 90 80 70 60 50 40 30 20 10 0 signal-to-(noise + distortion) (db) frequency (khz) 1 10 50 100 90 80 70 60 50 40 30 20 signal-to-(noise + distortion) (db) C40 C35 C30 C25 C20 C15 C10 C5 0 input level (db) 10 20 30 40 50 60 70 ?55 0 55 110 165 220 temperature (c) reference current (a) 5v2.7v
ads8320-ht sbas521b ? december 2010 ? revised september 2012 www.ti.com theory of operation the ads8320 is a classic successive approximation register (sar) analog-to-digital (a/d) converter. the architecture is based on capacitive redistribution, which inherently includes a sample/hold function. the converter is fabricated on a 0.6 cmos process. the architecture and process allow the ads8320 to acquire and convert an analog signal at up to 100,000 conversions per second while consuming less than 4.5 mw from+v cc . the ads8320 requires an external reference, an external clock, and a single power source (v cc ). the external reference can be any voltage between 500 mv and v cc . the value of the reference voltage directly sets the range of the analog input. the reference input current depends on the conversion rate of the ads8320. the external clock can vary between 24 khz (1-khz throughput) and 2.4 mhz (100-khz throughput). the duty cycle of the clock is essentially unimportant, as long as the minimum high and low times are at least 200 ns (v cc = 2.7 v or greater). the minimum clock frequency is set by the leakage on the capacitors internal to the ads8320. the analog input is provided to two input pins: +in and ? in. when a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. while a conversion is in progress, both inputs are disconnected from any internal function. the digital result of the conversion is clocked out by the dclock input and is provided serially, most significant bit first, on the d out pin. the digital data that is provided on the dout pin is for the conversion currently in progress ? there is no pipeline delay. it is possible to continue to clock the ads8320 after the conversion is complete and to obtain the serial data least significant bit first. see the digital timing section for more information. analog input the +in and ? in input pins allow for a differential input signal. unlike some converters of this type, the ? in input is not re-sampled later in the conversion cycle. when the converter goes into the hold mode, the voltage difference between +in and ? in is captured on the internal capacitor array. the range of the ? in input is limited to ? 0.1 v to 1 v ( ? 0.1 v to 0.5 v when using a 2.7-v supply). because of this, the differential input can be used to reject only small signals that are common to both inputs. thus, the ? in input is best used to sense a remote signal ground that may move slightly with respect to the local ground potential. the input current on the analog inputs depends on a number of factors: sample rate, input voltage, source impedance, and power-down mode. essentially, the current into the ads8320 charges the internal capacitor array during the sample period. after this capacitance has been fully charged, there is no further input current. the source of the analog input voltage must be able to charge the input capacitance (45 pf) to a 16-bit settling level within 4.5 clock cycles. when the converter goes into the hold mode or while it is in the powerdown mode, the input impedance is greater than 1 g . care must be taken regarding the absolute analog input voltage. to maintain the linearity of the converter, the ? in input should not drop below gnd ? 100 mv or exceed gnd + 1 v. the +in input should always remain within the range of gnd ? 100 mv to v cc + 100 mv. outside of these ranges, the converter linearity may not meet specifications. to minimize noise, low bandwidth input signals with lowpass filters should be used. reference input the external reference sets the analog input range. the ads8320 operates with a reference in the range of 500 mv to v cc . there are several important implications of this. as the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. this is often referred to as the least significant bit (lsb) size and is equal to the reference voltage divided by 65,536. this means that any offset or gain error inherent in the a/d converter will appear to increase, in terms of lsb size, as the reference voltage is reduced. the noise inherent in the converter also appears to increase with lower lsb size. with a 5-v reference, the internal noise of the converter typically contributes only 1.5 lsb peak-to-peak of potential error to the output code. when the external reference is 500 mv, the potential error contribution from the internal noise will be 10 times larger ? 15 lsbs. the errors due to the internal noise are gaussian in nature and can be reduced by averaging consecutive conversion results. 12 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: ads8320-ht
ads8320-ht www.ti.com sbas521b ? december 2010 ? revised september 2012 for more information regarding noise, consult the typical performance curve ? peak-to-peak noise vs reference voltage. ? note that the effective number of bits (enob) figure is calculated based on the converter ? s signal-to- (noise + distortion) ratio with a 1-khz, 0-db input signal. sinad is related to enob as follows: (1) with lower reference voltages, extra care should be taken to provide a clean layout including adequate bypassing, a clean power supply, a low-noise reference, and a low-noise input signal. because the lsb size is lower, the converter is also more sensitive to external sources of error such as nearby digital signals and electromagnetic interference. noise the noise floor of the ads8320 itself is extremely low, as can be seen in figure 19 and figure 20 , and is much lower than competing a/d converters. it was tested by applying a lownoise dc input and a 5-v reference to the ads8320 and initiating 5000 conversions. the digital output of the a/d converter varies in output code due to the internal noise of the ads8320. this is true for all 16-bit sar-type a/d converters. using a histogram to plot the output codes, the distribution should appear bell-shaped with the peak of the bell curve representing the nominal code for the input value. the 1 , 2 and 3 distributions represents the 68.3%, 95.5%, and 99.7%, respectively, of all codes. the transition noise can be calculated by dividing the number of codes measured by 6 and this yields the 3 distribution or 99.7% of all codes. statistically, up to 3 codes could fall outside the distribution when executing 1000 conversions. the ads8320, with < 3 output codes for 3 distribution, yields a < 0.5 lsb transition noise. remember, to achieve this low noise performance, the peak-to-peak noise of the input signal and reference must be < 50 v. figure 19. histogram of 5000 conversions of a dc input at the code transition copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 13 product folder links: ads8320-ht 2 2510 3 2490 4 code 5 6 0 0 0 0 1 sinad = enob 6.02 + 1.76
ads8320-ht sbas521b ? december 2010 ? revised september 2012 www.ti.com figure 20. histogram of 5000 conversions of a dc input at the code center 14 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: ads8320-ht 2 72 3 4864 4 code 5 6 64 0 0 0 1
ads8320-ht www.ti.com sbas521b ? december 2010 ? revised september 2012 digital interface signal levels the digital inputs of the ads8320 can accommodate logic levels up to 5.5 v regardless of the value of v cc . thus, the ads8320 can be powered at 3 v and still accept inputs from logic powered at 5 v. the cmos digital output (d out ) swings 0 v to v cc . if v cc is 3 v and this output is connected to a 5-v cmos logic input, then that ic may require more supply current than normal and may have a slightly longer propagation delay. serial interface the ads8320 communicates with microprocessors and other digital systems via a synchronous 3-wire serial interface, as shown in figure 21 and table 2 . the dclock signal synchronizes the data transfer with each bit being transmitted on the falling edge of dclock. most receiving systems will capture the bitstream on the rising edge of dclock. however, if the minimum hold time for d out is acceptable, the system can use the falling edge of dclock to capture each bit. a falling cs signal initiates the conversion and data transfer. the first 4.5 to 5.0 clock periods of the conversion cycle are used to sample the input signal. after the fifth falling dclock edge, d out is enabled and outputs a low value for one clock period. for the next 16 dclock periods, d out outputs the conversion result, most significant bit first. after the least significant bit (b0) has been output, subsequent clocks repeat the output data but in a least significant bit first format. after the most significant bit (b15) has been repeated, d out will tri-state. subsequent clocks will have no effect on the converter. a new conversion is initiated only when cs has been taken high and returned low. table 2. timing specifications (v cc = 2.7 v and above, ? 55 c to 210 c) symbol description min typ max unit t smpl analog input sample time 4.5 5 clk cycles t conv conversion time 16 clk cycles t cyc throughput rate 100 khz t csd cs falling to dclock low 0 ns t sucs cs falling to dclock rising 20 ns t hdo dclock falling to current d out not valid 5 15 ns t ddo dclock falling to next d out valid 30 50 ns t dis cs rising to d out tri-state 70 100 ns t en dclock falling to d out enabled 20 50 ns t f d out fall time 5 25 ns t r d out rise time 7 25 ns data format the output data from the ads8320 is in straight binary format, as shown in table 3 . this table represents the ideal output code for the given input voltage and does not include the effects of offset, gain error, or noise. table 3. ideal input voltages and output codes digital output straight binary description analog value binary code hex code full-scale range v ref least significant bit (lsb) v ref /65,536 full scale v ref ? 1 lsb 1111 1111 1111 1111 ffff midscale v ref /2 1000 0000 0000 0000 8000 midscale ? 1 lsb v ref /2 ? 1 lsb 0111 1111 1111 1111 7fff zero 0 v 0000 0000 0000 0000 0000 copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 15 product folder links: ads8320-ht
ads8320-ht sbas521b ? december 2010 ? revised september 2012 www.ti.com power dissipation the architecture of the converter, the semiconductor fabrication process, and a careful design allow the ads8320 to convert at up to a 100-khz rate while requiring very little power. still, for the absolute lowest power dissipation, there are several things to keep in mind. the power dissipation of the ads8320 scales directly with conversion rate. therefore, the first step to achieving the lowest power dissipation is to find the lowest conversion rate that satisfies the requirements of the system. in addition, the ads8320 is in power-down mode under two conditions: when the conversion is complete and whenever cs is high (as shown in figure 21 ). ideally, each conversion should occur as quickly as possible, preferably at a 2.4-mhz clock rate. this way, the converter spends the longest possible time in the power-down mode. this is very important as the converter not only uses power on each dclock transition (as is typical for digital cmos components), but also uses some current for the analog circuitry, such as the comparator. the analog section dissipates power continuously, until the power-down mode is entered. figure 21. ads8320 basic timing diagrams 16 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: ads8320-ht cs/shdn d out dclock complete cycle power down conversion sample use positive clock edge for data transfer t sucs t conv t smpl note: minimum 22 clock cycles required for 16-bit conversion. shown are 24 clock cycl es. if cs remains low at the end of conversion, a new datastream with lsb-first is shi fted out again. b15 (msb) (lsb) b7 b1 b6 b2 b5 b3 b4 hi-z 0 hi-z t csd b14 b13 b12 b11 b10 b9 b8 b0
ads8320-ht www.ti.com sbas521b ? december 2010 ? revised september 2012 figure 22. timing diagrams and test circuits for the parameters in table 2 figure 23 shows the current consumption of the ads8320 versus sample rate. for this graph, the converter is clocked at 2.4 mhz regardless of the sample rate ? cs is high for the remaining sample period. figure 24 also shows current consumption versus sample rate. however, in this case, the dclock period is 1/24th of the sample period ? cs is high for one dclock cycle out of every 16. copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 17 product folder links: ads8320-ht d out 1.4v test point 3k 100pfc load load circuit for t ddo , t r , and t f voltage waveforms for d out rise and fall times, t r , t f voltage waveforms for d out delay times, t ddo voltage waveforms for t dis notes: (1) waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control. (2) waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control. voltage waveforms for t en load circuit for t dis and t en t r d out v oh v ol t f d out test point t dis waveform 2, t en v cc t dis waveform 1 100pfc load 3k t dis cs/shdn d out waveform 1 (1) d out waveform 2 (2) 90% 10% v ih 4 1 b11 5 t en cs/shdn dclock v ol d out t ddo d out dclock v oh v ol v il t hdo
ads8320-ht sbas521b ? december 2010 ? revised september 2012 www.ti.com figure 23. maintaining f clk at the highest possible rate allows supply current to drop linearly with sample rate figure 24. scaling f clk reduces supply current only slightly with sample rate there is an important distinction between the power-down mode that is entered after a conversion is complete and the full power-down mode which is enabled when cs is high. cs low will shut down only the analog section. the digital section is completely shut down only when cs is high. thus, if cs is left low at the end of a conversion and the converter is continually clocked, the power consumption will not be as low as when cs is high. figure 25 shows more information. figure 25. shutdown current with cs high is 50 na typically, regardless of the clock. shutdown current with cs low varies with sample rate 18 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: ads8320-ht 1000 800600 400 200 0.0 0.00 supply current ( m a) sample rate (khz) t a = 25 c v cc = 5.0v v ref = 5.0v f clk = 24 ? f sample cs low (gnd) cs high (v cc ) 0.250 0.1 1 10 100 1000 100 10 1 supply current ( a) sample rate (khz) t a = 25 c v cc = 5.0v v ref = 5.0v f clk = 24 ? f sample 0.1 1 10 100 1000 100 10 1 supply current (a) sample rate (khz) v cc = 5.0v v ref = 5.0v v cc = 2.7v v ref = 2.5v t a = 25 c f clk = 2.4mhz 0.1 1 10 100
ads8320-ht www.ti.com sbas521b ? december 2010 ? revised september 2012 power dissipation can also be reduced by lowering the power-supply voltage and the reference voltage. the ads8320 operates over a v cc range of 2.0 v to 5.25 v. however, at voltages below 2.7 v, the converter will not run at a 100-khz sample rate. see the typical performance curves for more information regarding power supply voltage and maximum sample rate. short cycling another way of saving power is to utilize the cs signal to short cycle the conversion. because the ads8320 places the latest data bit on the d out line as it is generated, the converter can easily be short cycled. this term means that the conversion can be terminated at any time. for example, if only 14 bits of the conversion result are needed, then the conversion can be terminated (by pulling cs high) after the 14th bit has been clocked out. this technique can be used to lower the power dissipation (or to increase the conversion rate) in those applications where an analog signal is being monitored until some condition becomes true. for example, if the signal is outside a predetermined range, the full 16-bit conversion result may not be needed. if so, the conversion can be terminated after the first n bits, where n might be as low as 3 or 4. this results in lower power dissipation in both the converter and the rest of the system, as they spend more time in the power-down mode. copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 19 product folder links: ads8320-ht
ads8320-ht sbas521b ? december 2010 ? revised september 2012 www.ti.com layout (1) for optimum performance, care should be taken with the physical layout of the ads8320 circuitry. this is particularly true if the reference voltage is low and/or the conversion rate is high. at a 100-khz conversion rate, the ads8320 makes a bit decision every 416 ns. that is, for each subsequent bit decision, the digital output must be updated with the results of the last bit decision, the capacitor array appropriately switched and charged, and the input to the comparator settled to a 16-bit level all within one clock cycle. the basic sar architecture is sensitive to spikes on the power supply, reference, and ground connections that occur just prior to latching the comparator output. thus, during any single conversion for an n-bit sar converter, there are n ? windows ? in which large external transient voltages can easily affect the conversion result. such spikes might originate from switching power supplies, digital logic, and high power devices, to name a few. this particular source of error can be very difficult to track down if the glitch is almost synchronous to the converter dclock signal ? as the phase difference between the two changes with time and temperature, causing sporadic misoperation. with this in mind, power to the ads8320 should be clean and well bypassed. a 0.1- f ceramic bypass capacitor should be placed as close to the ads8320 package as possible. in addition, a 1- f to 10- f capacitor and a 5- or 10- series resistor may be used to low-pass filter a noisy supply. the reference should be similarly bypassed with a 0.1- f capacitor. again, a series resistor and large capacitor can be used to low-pass filter the reference voltage. if the reference voltage originates from an op amp, be careful that the op amp can drive the bypass capacitor without oscillation (the series resistor can help in this case). keep in mind that while the ads8320 draws very little current from the reference on average, there are still instantaneous current demands placed on the external input and reference circuitry. texas instruments' opa627 op amp provides optimum performance for buffering both the signal and reference inputs. for low-cost, low-voltage, single-supply applications, the opa2350 or opa2340 dual op amps are recommended. also, keep in mind that the ads8320 offers no inherent rejection of noise or voltage variation in regards to the reference input. this is of particular concern when the reference input is tied to the power supply. any noise and ripple from the supply will appear directly in the digital results. while high-frequency noise can be filtered out as described in the previous paragraph, voltage variation due to the line frequency (50 hz or 60 hz), can be difficult to remove. the gnd pin on the ads8320 should be placed on a clean ground point. in many cases, this will be the ? analog ? ground. avoid connecting the gnd pin too close to the grounding point for a microprocessor, microcontroller, or digital signal processor. if needed, run a ground trace directly from the converter to the power-supply connection point. the ideal layout includes an analog ground plane for the converter and associated analog circuitry. (1) opa627, opa2350 and opa2340 have not been characterized or tested at 210 c. 20 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: ads8320-ht
ads8320-ht www.ti.com sbas521b ? december 2010 ? revised september 2012 application circuits figure 26 shows a basic data acquisition system. the ads8320 input range is 0 v to v cc , as the reference input is connected directly to the power supply. the 5- resistor and 1- f to 10- f capacitor filter the microcontroller ? noise ? on the supply, as well as any high-frequency noise from the supply itself. the exact values should be picked such that the filter provides adequate rejection of the noise. figure 26. basic data acquisition system copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 21 product folder links: ads8320-ht ads8320 v cc cs d out dclock v ref +in Cin gnd + + 5 1f to 10f 1f to 10f 0.1f microcontroller 2.7v to 5.25v
package option addendum www.ti.com 31-may-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) device marking (4/5) samples ads8320shkj active cfp hkj 8 1 tbd call ti n / a for pkg type -55 to 210 ads8320s hkj ADS8320SHKQ active cfp hkq 8 1 tbd au n / a for pkg type -55 to 210 ads8320s hkq ads8320skgd1 active xcept kgd 0 240 tbd call ti n / a for pkg type -55 to 210 ads8320skgd2 active xcept kgd 0 10 tbd call ti n / a for pkg type -55 to 210 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 31-may-2013 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of ads8320-ht : ? catalog: ads8320 note: qualified version definitions: ? catalog - ti's standard catalog product

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